MEGACHIPS ASIC TECHNOLOGY

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5G RU ASIC SOLUTIONS

Lower power and lower cost ASIC solutions for 5G RU

The “FPGA + discrete AFE” solution is the quickest way to build 5G RU system for proof-of-concept and/or early deployment purpose. However, there are challenges in terms of power consumption and cost. MegaChips 5G RU ASIC solutions, taking advantage of FPGA to ASIC conversion and high-end IP (like high-speed data converter) integration experience over three decades, enable lower power and lower cost 5G RU system for high-volume mass production.

Applications: 5G RU

Sub 6G and/or mmWave macro cell
Sub 6G and/or mmWave small
mmWave smart repeater

FPGA to ASIC Conversion

Smooth conversion without compromising performance

FPGA to ASIC conversion for 5G RU

MegaChips 5G RU ASIC solutions offer FPGA, which is a very power-hungry and expensive component, to ASIC conversion which enables customers’ system to be more cost-efficient and save power consumption up to 55% without compromising customer’s system performance.

To mitigate risks and make this conversion smooth, MegaChips offers two steps approach.

Step1: Analog test chip development

Ensuring analog IPs especially high-speed data converters work properly in the customers’ system at the early stage is a key to success of this conversion. For this purpose, MegaChips offers to develop the analog test chip which allows customers to test/evaluate analog IPs with their FPGA in their system. This will help to mitigate risks of unexpected performance of the final chip.

Step2: Final single chip development

Once the analog IPs’ performance/characteristics are confirmed at the system level test/evaluation, MegaChips converts user logic in FPGA to ASIC and consolidate it and the analog test chip into a single chip.

Up to 55% power saving

Data bus between discrete AFE and FPGA significantly contributes to a large proportion of total power consumption and this proportion is growing because of the larger amount of RX/TX channels and/or massive MIMO. MegaChips FPGA to single chip ASIC conversion enables to save up to 55% of power consumption by eliminating this data bus.

16T16R Discreate AFE + FPGA JESD		16T16R Singe chip asic in 7 nm
FPGA JESD	4W (250mW x 16 ch)	AFE	10W
Discrete AFE	18W (4.5W x 4 chips)
Total	22W	Total	10W

Available technology node

TSMC: 28nm, 16nm FFC, 5/7nm(planning)

GF: 22nm FDSOI, 12nm FDSOI(planning)

5G RU IP Roadmap

MegaChips will deliver the best fit custom IPs by taking into account RF signal spectrum bands, signal bandwidth, signal conversion (zero-IF, direct RF), communication protocol and so on.

RF	Modem and L1
High-speed ADC/DAC	eCPRI Frame Mux
DUC / DDC	Tx / Rx U Plane Processing
Digital AGC	Rx C Plane Processing
Digital LPF	M Plane Processing
Digital Channel Filter	U Plane framer
Digital Spectral Analyzer	U Plane De Framer
pFIR / cFIR Filter	C Plane De Mux
Digital Gain / Attenuation	Uplink / Downlink C Plane Management
CIC Decimation Filter	PRACH
DC Offset Correction	5G FFT + CP Removal
Quadrature Error Correction (IQ Imbalance)	IQ Decomposition
	Layer Mapping
	Pre Coding
	Beamforming

Comprehensive 5G RU ASIC development supports

From product definition to mass-production

Besides typical ASIC development supports like ASIC test/final chip development and ASIC production, MegaChips is offering development supports for the earlier development/design phases like production definition and FPGA development to customers who don’t have experience in chip development. This comprehensive support helps not only chip vendors but system/module vendors to add more value to their products and make it more cost-competitive.

Contact Us

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