MEGACHIPS ASIC TECHNOLOGY

We Bring Ideas to Silicon

Create what you imagine and transform the world we live in with MegaChips ASIC technology

ASIC TURNKEY SERVICES

MegaChips is dedicated to bringing your ideas to production; supporting your design from specification to tape out.

Why MegaChips — Process Technology — Design Flow — Intellectual Property — Packaging Technology — Testing — Embedded Memory — Join ASIC developers

Why MegaChips For Your ASIC/SoC?

Advanced ASIC technology

Leading Global Semiconductor Supplier
- 26 years experience with ~1,500 designs
- Stable long term business model
- Flexible engagement model
Extensive Expertise and Engineering resources
- Access to US engineering and Global expertise
- Fab and Manufacturing expertise
Access to extensive eco system and IPs
- Proven ability to deliver customer specific IP
- Proven 1st time success track record
Single point of contact for all aspects of SoC development
- Design Methodology, IP’s ( design qualification, integration)
- Wafer Manufacturing, Assembly, Test
- Product engineering, Quality & Reliability
- WW Supply chain management

Affordable

Highly efficient manufacturing
- Focused on core competencies (design center, full-custom IP development, including SerDes, quality and reliability and supply chain management)
Economies-of-scale
- Via large unit volumes shipped to consumer and LCD display customers (leads to lower costs)

Process Technology

MegaChips is a pioneer in the ASIC industry in using foundries. In 1997 we adopted a fabless business model for advanced process technologies. The fabless ASIC supplier model is being adopted by many of our competitors today – we have a decade of experience with it! The benefit to customers of this 10-years of experience include on-time delivery through a smooth supply chain and affordable prices through strong relationships with our fab partners.

MegaChips works with and sources from multiple foundries such as TSMC, UMC, GlobalFoundries, Samsung, and STMicro to achieve the ultimate combination of low power, high performance, high yield and exceptional reliability at the lowest cost.

MegaChips Process Technologies

Product Family	Geometry (Drawn)	Core Voltage (V)	I/O Voltage (V)	Max. Metal Layers	Gate Density (Kgates/ mm2)	Fab
Standard Cell
K28HPC	28nm	0.9 HPC	2.5/1.8	10	4500	Multiple
K40G K40L	40nm	0.9 GP 1.1 LP	3.3/2.5/1.8	10	1620	Multiple
K65G K65L	65nm	1.0 GP 1.2 LP	3.3/2.5/1.8	9	854	TSMC
KS8500	90nm	1.0*	3.3/2.5	9	457	TSMC
KS7500	0.13μm	1.2	3.3/2.5	8	256	TSMC
KS6500	0.15μm	1.5	3.3	7	180	UMC
KS6000	0.18μm	1.8	3.3	6	94	UMC & He Jian

* Supports Voltage Islands

High Density Libraries

Process technology is just one part of the story – libraries are the other part. MegaChips’s 7-grid libraries provide higher gate densities
than those of competitors:

ASIC Supplier	0.13µm Standard Cell Library Density (Kgates/mm2)	Source
MegaChips	256	MegaChips
IBM	175 (MegaChips is 46% denser)	Source Link
ST	200 (MegaChips is 28% denser)	Source Link

Virage Logic is the source for MegaChips’s 7-grid libraries. MegaChips helped Virage develop their 7-grid ASAP Logic Ultra-High Density (UHD)
libraries. By compacting cells into a 7-high grid, MegaChips libraries are able to achieve higher gate densities than 8-grid (or higher)
libraries used by competitors. The benefit to customers of our higher density libraries is lower unit costs.

MegaChips “Rainbow Wafer”

Another important differentiation between MegaChips and some other fabless ASIC suppliers is the process we follow to validate the design of physical
IP (such as SerDes, PLLs, etc.) before allowing it to be used by our customers. MegaChips uses “Rainbow Wafers” to ensure that any physical
IP in our IP portfolio will work over the entire valid process spectrum:

Figure 1: MegaChips Rainbow Wafer

Design Flow

The MegaChips Team: It’s Not the Tools, It’s How They’re Used

Of all aspects of an ASIC project, design flow places the heaviest demands on a customer’s design engineers and requires the closest teamwork between the customer and provider. Consequently, the design flow provides the best opportunity to distinguish MegaChips from its competitors and for customers to enjoy the most conspicuous benefits. For example, while all providers use standard electronic design automation (EDA) tools, the real challenge lies in using these tools to create a flow that is smooth and efficient from the customer’s perspective. For example, each process technology has idiosyncrasies that affect design implementation, and only experienced ASIC design center engineers understand how to use their EDA tools to obtain optimal results and minimize demands upon customers.

ASIC Development Flow and Support Tools

ASIC Intellectual property

By using IP from MegaChips’s extensive IP portfolio, customers can complete their ASIC designs faster, enabling their product to get to market faster.

MegaChips’s corporate strategy is to focus on our core competencies and work with partners for other items. A core competency for MegaChips is developing physical IP, such as SerDes, PLLs, CDRs, ADCs, DACs, etc. Key features of MegaChips’s physical IP include:

VHDL/Verilog models for simulation during design.
MegaChips test chips to prove the designs in silicon.
Guaranteed (fixed) timing in hard layout when necessary.
Static timing analysis support to verify performance.
High fault coverage by means of pre-generated test vectors

Digital IP, which can easily be synthesized to target any ASIC technology, is readily available from a wide variety of sources today. The digital IP in MegaChips’s IP portfolio is acquired from established, well-known partners such as ARM, MIPS, CEVA, StarCore, Mentor, etc.

MegaChips IP Partners Program

IP strategy Icon Unfortunately, a key obstacle to the proliferation of third-party digital IP is the negotiation of license agreements, which can take more time to complete than the technical evaluation of the IP, delaying the ASIC’s project schedule in the process.

To simplify the usage of third-party digital IP, MegaChips has negotiated license agreements with selected third-party IP suppliers, its “IP Partners”. Customers who select IP from MegaChips’s IP Partners can be assured that MegaChips can quickly acquire the IP on their behalf, speeding their ASIC’s time-to-market. MegaChips’s IP Partners include ARM, MIPS, CEVA, Mentor Graphics, Mysticom, SafeNet, and Sonics.

Advanced Packaging Technology

In many modern ASICs, the design of the package is as important as the design of the ASIC itself. MegaChips has extensive packaging experience, including:

High-performance, flip-chip BGAs with ball counts in excess of 2000 balls,
Multi-chip modules (MCMs) – multiple die in a single package
Multi-package modules (MPMs) – multiple packaged devices put together in a single package

Stacked BGAs

MegaChips designs redistribution layers (RDLs) and BGA substrates itself, ensuring the final packaged device performs as expected. Design techniques we employ in RDL and substrate design include:

Using substrate routing to overcome RDL trace length differences
Specifying tolerances for substrate routing – example, Bus[31:0] to be within 1 mm of each other
Using zig-zag routing to match lengths between different signals

Figure 1: MegaChips RDL Routing

Figure 2: MegaChips Substrate Routing

Figure 3: MegaChips MPM

Figure 4: MegaChips Stacked BGA

Testing

MegaChips’s ASIC testing methodology includes full scan insertion, memory BIST insertion, and Iddq testing. In addition to performing final high-speed testing, MegaChips also supports JTAG boundary scan register (BSR) insertion. Our state-of-the-art test center has dozens of test machines – including state-of-the-art Advantest and HP testers.

Scan

To help identify manufacturing defects, MegaChips is able to insert scan chains into the ASIC as a service to our customers. To minimize the effects of scan insertion on performance, we provide customers with pre-scan libraries that incorporate the effects of scan insertion on performance and die area. MegaChips also uses proprietary tools to prevent scan chain shift errors. We create vectors from the scan chain, which we use to test the ASIC before shipment to customers. MegaChips’s scan insertion techniques ensure very high fault coverage.

BIST

MegaChips uses BIST to test its memories for manufacturing defects. Our controller adds minimal overhead (about 1,000 gates) and a single controller supports dozens of memory blocks. Multiple controllers can be instantiated into hierarchical designs.

Iddq Testing

MegaChips uses advanced Iddq testing to help identify manufacturing defects in its ASICs. We use automatic address selection techniques to measure thousands of addresses. We also utilize fast DC measurement techniques to conduct Iddq testing in a quick and cost effective manner.

JTAG (IEEE 1149.1 compatible)

MegaChips’s JTAG support includes providing customers with the Test Access Port Controller, and BSDL files.

Embedded Memory

ASIC Memories

In response to the demand for high-performance embedded memory, MegaChips offers a range of options that can be embedded into any ASIC – each delivering the efficiency that only on-chip memory provides. These options – which include single-port and dual-port SRAM, DRAM, and ROM (some with high-speed and write per bit and byte options) – are available for any application, and they are available in a variety of sizes, configurations, access times, and cycle times.

Memory Interface

IP Type	Process Node
	130nm	110nm	90nm	55nm	65nm	40nm	28nm
DDR2/3,LPDDR2 PHY	DDR2	✔	✔		✔	✔	✔
DDR4 Phy							✔
NAND Flash		✔		✔			✔
Error Correction	✔	✔	✔	✔	✔	✔	✔
Encryption (AES, RSA,etc)	✔	✔	✔	✔	✔	✔	✔