Analog Front End (AFE) IC for broadband communication

The KAN1101 is a high performance, low power, and cost-effective solution for home networking, and wireless base station applications.

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KAN1101 is among MCC’s high-end integrated analog front end (AFE series) family of products. KAN1101 provides high performance, low power, and cost effective solution for home networking applications, wireless base station, and so on. KAN1101 integrates two analog-to-digital converters (ADC), programmable gain amplifier (PGA), analog channel equalizer (ACE), one digital-to-analog converters (DAC), one current amplifiers (IAMP), one clock synthesizer (LC-based), one 3.312Gbps serializer/deserializer (SerDes), serial peripheral interface (SPI), and digital signal processing units (DSP). KAN1101 is available in 65nm CMOS technology.

The figure below shows the AFE overall block diagram. PGA has the function of ACE to compensate higher frequency signals which are largely attenuated over long distance which usually results in lower SNR on receiver side. DAC is 12-bit 424Msps. Two ADCs are identical and operating at 12-bit 212Msps to achieve 12-bit 424 Msps by means of time interleaved manner. The 12-bit sampling data is transferred between the baseband (Digital PHY) chip and KAN1101 via the SerDes at 3.312Gbps serial bit stream. A simple protocol to convert the 12-bit to the serial bit stream and vice versa is defined as the ASI (AFE Serial Interface), which is compatible with JESD 204A (JEDEC standard, serial interface for converters). The ASI defines framing, scrambling, 8B/10B coding, establishing and maintaining the 3.312Gbps link. The serial interface, as adopted by many similar standards provides a number of advantages which include simpler PCB design, reduced EMI, lower pin counts, etc. Tx can provide a full scale current in the range of 4mA to 200mA by IAMP. IAMP can be bypassed. Note that either IAMP enabled or bypassed can be chosen at a time (these are exclusive). The PGA gain can be configured from -18 dB to 24 dB. The clock synthesizer is an LC-VCO based PLL technology with low jitter employing the 35.328MHz Xtal input as its reference clock. The sampling clocks and the differential reference clock to the SerDes are derived from the PLLs and are carefully routed to maintain the signal quality and integrity. The differential reference clock is also output on IFCKOP/N through LVDS driver. The frequency of the differential clock is 132.48MHz. It shall be used as the reference clock of the SerDes in a baseband chip for ASI.

The digital signal processing units realize FIR filters, such as pre-emphasis, interpolator, decimator, and calibrations for DAC, PGA, and ADCs. The DSP units are among the important blocks within KAN1101 to maintain the utmost performance. KAN1101 provides the optimum control for power consumption within the device by switching on/off each component’s operation. The target system can be optimized by configuring KAN1101 via the three or four wire SPI Interface.

Features

• 65nm CMOS Wide Band AFE IC
• 12mm x 12mm VQFN 88-pin 0.5mm pitch, or, 10mm x 10mm VQFN 88-pin 0.4mm
• High speed sampling rate and low power
• High resolution and wide frequency range
• Deep Sleep Mode Operation
• Up to 212 Msps data rate

Tx DAC path

• 12-bit 424Msps DAC
• Pre-emphasis filter
• Selectable low pass ( 0-95.4MHz or 0-100MHz ) and high pass ( 116.6MHz-212MHz or 112-212MHz ) mode 2x interpolator
• Integrated 200mA line driver with 20dB gain control (bypass mode is supported)

Rx ADC path

• 12-bit 424Msps by means of 2x 12-bit 212 Msps ADC with time interleaved manner
• Low-noise PGA with ACE
• Selectable low pass ( 0-95.4MHz or 0-100MHz ) and high pass ( 116.6MHz-212MHz or 112-212MHz ) mode /2 decimator
• Integrated low-jitter clock synthesizer (PLL)
• 3.312Gbps high speed serial interface as the digital interface (compatible with JESD204A)
• IFCKOP/N are the clean 132.48MHz clock output to be used as the reference clock for a baseband chip
• Integrated fine and accurate foreground calibration on TxDAC and RxADC path

Downloads

KAN1101 Wideband Analog Front End IC Data Brief (270 KB)

The KHN11112 is a highly integrated analog front-end IC (AFE) for the home networking applications such as HomePNA and broadband PLC (HD-PLC, HPAV, etc). Data rates up to 80MSPS are supported in both Rx and Tx path. SPI (serial peripheral I/F) allows software programmability of the AFE.

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The KHN1112 is a highly integrated analog front-end IC (AFE) for the home networking applications such as HomePNA and broadband PLC (HD-PLC, HPAV, etc). Data rates up to 80MSPS are supported in both Rx and Tx path. SPI (serial peripheral I/F) allows software programmability of the AFE.

The functional block diagram of the KHN11112 is shown below. The Tx signal path consists of a x2 low-pass interpolation filter, SSB modulator, 12-bit 160MSPS DAC. The Rx signal path consists of a programmable amplifier (PGA), a 160MSPS ADC and a decimation filter to generate a 80MSPS digital output word. On-chip PLL multiplier and synthesizer provide all the required clock signals from a single crystal or clock source.

The 12-bit digital data interface runs maximum of 80MHz in half-duplex mode, and up to 108MHz in full duplex mode.

The KHN11121 is available in a 64 Quad Flat No-Lead package (VQFN), 9mmx9mm with 0.5mm pin pitch. It is specified over the industrial temperature range of -40°C to +85°C

Features

• Home Networking Analog Front End IC covering broadband PLC (HD-PLC, HPAV, etc) and HomePNA 3.1
• High speed sampling rate and low power consumption
• Up to 80MSPS data rate

Tx path

• 12bit 160MSPS DAC
• x2 interpolation filter
• Configurable SSB modulation
• Maximum 10dBm current-source DAC with 0.5dB gain step

Rx path

• 12bit 160MSPS ADC
• Configurable SSB modulation
• -18 dB to +42dB low-noise PGA
• 14MHz – 52MHz configurable LPF cutoff frequency
• Internal clock multiplier (PLL)
• Integrated fine and accurate foreground calibration on Tx and Rx path
• 64 Exposed Quad Flat No-Lead package (VQFN)
• Industrial Temp range (-40 ~+85⁰C)

Product Brochure

The KHN1121/KHN1122 is a highly integrated analog front-end IC (AFE) for the home networking applications such as G.hn, HomePNA or Powerline communication. Data rates up to 200MSPS are supported in both Rx and Tx path. The on-chip PLL multiplier and synthesizer provide all the required clock signals from a single crystal or clock source.

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The KHN1122 is a highly integrated analog front-end IC (AFE) for the home networking applications such as G.hn, HomePNA or Powerline communication. Data rates up to 200MSPS are supported in both Rx and Tx path. The on-chip PLL multiplier and synthesizer provide all the required clock signals from a single crystal or clock source.

The functional block diagram of the KHN1122 is shown below. The device can be configurable for either SISO (single channel configuration) or MIMO (2 channel configuration).

The Tx signal path consists of a x2 low-pass interpolation filter, 12-bit 400MSPS DAC1, 10-bit 200MSPS DAC2 and 2 line drivers (IAMP_1/2). For SISO, the TX path is using the DAC1 with 400MSPS.

The Rx signal path consists of a programmable gain amplifier (PGA), a 400MSPS ADC (2x 200MSPS ADCs for MIMO) and a decimation filter to generate a 200MSPS digital output word (100MSPS digital output word for MIMO).

Features

Product Brochure

The KHN1131/1132 is a highly integrated analog front-end IC (AFE) for the home networking applications such as G.hn, HomePNA or Powerline communication. Data rates up to 200MSPS are supported in both Rx and Tx path. The on-chip PLL multiplier and synthesizer provide all the required clock signals from a single crystal or clock source.

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The KHN1132 is a highly integrated analog front-end IC (AFE) for the home networking applications such as G.hn, HomePNA or Powerline communication. Data rates up to 200MSPS are supported in both Rx and Tx path. The on-chip PLL multiplier and synthesizer provide all the required clock signals from a single crystal or clock source.
The functional block diagram of the KHN1132 is shown below. The Tx signal path consists of a x2 low-pass interpolation filter, 12-bit 400MSPS DAC, and line driver (Iamp). The Rx signal path consists of a programmable gain amplifier (PGA), a 400MSPS ADC and a decimation filter to generate a 200MSPS digital output word.

A 3.125GHz AFE SerDes interface (ASI) with the digital back-end provides 200MSPS data rate. Not only digital data transfer but also commands can be sent via ASI.

Features

Product Brochure

The KHN11401 is a highly integrated analog front-end IC for the home networking applications such as Power-line communication(PLC), Smart Grid and IEEE1901.

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The KHN11401 is a highly integrated analog front-end IC for the home networking applications such as Power-line communication(PLC), Smart Grid and is the ideal for IEEE1901 the international standard for PLC communications. Data rate is supported up to 80MSPS and 160MSPS in Rx path and TX path, respectively. The digital interface provides full-duplex and half-duplex operation. Interfacing can be either binary or twos compliment, LSB or MSB first. A serial peripheral interface (SPI) allows software programmability of the front-end. An on-chip PLL multiplier and synthesizer provide all the required clock signals from a single crystal or clock source.

The functional block diagram of the KHN11401 is shown below. The Tx signal path consists of a bypassable x2 low-pass interpolation filter, 10-bit TxDAC and a current amplifier (IAMP). The output current of KHN11401 can deliver up to 20mA full scale. Tx power can be controlled over a 7.5dB range in 0.5dB steps.

The Rx signal path consists of a programmable gain amplifier (RxPGA), LPF and a 10-bit ADC. The low-noise RxPGA has a programmable gain range of -18dB to +41dB in 1dB steps. Its input referred noise is less than 4nV/√Hz for gain settings beyond 30dB.

The KHN11401 is available in a 64 Exposed Quad Flat No-lead package, and are specified over the industrial temperature range of -40°C to +85°C

Features